1. Field of the Invention
The present invention relates to a method for implementing a serialization construct within an environment of parallel data flow graphs.
2. Description of the Related Art
Data flow graphs are used to implement operations taking place in order to verify the correct functional behavior of a logic design for an electronic circuit. An example is a main memory read operation in a computer system, wherein a data flow graph implementation consists of a node and an address. Said node controls signals of the logic design. The address is applied to the main memory while a following node receives and checks the data provided by the main memory.
A test generator which is used in the logic design verification can continuously generate data flow graphs with different operations. The data flow graphs can be chained together, so that a data flow graph chain represents a sequence of randomly selected operations. An environment of parallel data flow graphs allows the parallel execution of the data flow graphs. Thus, multiple data flow graph chains are usually running in parallel.
The patent application US 2006/0195732 A1, incorporated herein by reference, describes an integrated verification framework for concurrent execution of random and deterministic test cases. This is a data flow architecture, wherein random and deterministic test sequences are modeled into data flow graphs and executed in parallel. The verification framework does not contain a way to serialize the execution into a single test sequence. All active data flow graphs are executed independent of each other.
Such a serialization is required for some applications. For example, for the verification of an address translation unit in a processor design where such a framework is used, a serial construct is required. In the known IBM System z mainframe computing system, such serial construct is needed because changes to an address mapping table used for the dynamic address translation from virtual to real addresses must be done by one processor only. In this case all other processors using the same translation space must be stopped until an address mapping table update is completed.
In the environment described above, the only way to achieve this behavior is to signal a quiesce request to all test case generators in the environment in order to prevent a generation of new test sequences until the quiesce operation is finished. The drawback of this approach is that its implementation is specific for this application. But the number and type of test case generators depend on the device under verification. Its implementation breaks the data flow concept of the underlying framework.
It is therefore an object of the present invention to provide an improved method for implementing a serialization construct within an environment of parallel data flow graphs.